1. Field of the Invention
The present invention relates to a method for simulating a power distribution of a semiconductor integrated circuit, and a simulation program. In particular, the invention relates to a method for simulation in connection with initial estimation of power voltage drop, and a simulation program therefor.
2. Description of Related Art
Recently, in line with miniaturization in LSI development, large scaling of incorporated gate sizes and complexity thereof have been advanced, wherein such a problem arises that the period of development is lengthened. Therefore, in an attempt to shorten the period of development, in the stage of initial estimation before commencing the design, it becomes necessary to examine the power specifications by which power voltage drop is accommodated within a permissible range.
In Japanese Unexamined Patent Application Publication No. 2003-233637, a power wiring area of a semiconductor integrated circuit is divided into small areas of a so-called power unit, and a resistance value and a consumption current value of the power units are given, wherein a static voltage drop (static IR drop) is simulated by a constant consumption current value. Also, in Japanese Unexamined Patent Application Publication No. 2004-234618 as well, a resistance value, a consumption current value, an inductance value, and a capacitance value are given to the power units, wherein a dynamic power voltage distribution (dynamic IR drop) is simulated.